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DS1990A Serial Number iButtonTM
www.dalsemi.com
DS1990A SPECIAL FEATURES
Upgrade of DS1990 allows multiple Serial Number iButtons to reside on a common bus Unique 48-bit serial number Low-cost electronic key for access control 8-bit CRC for checking data integrity Can be read in less than 5 ms Operating temperature range of -40C to +85C Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike Multidrop controller for MicroLAN Digital identification by momentary contact Chip-based data carrier compactly stores information Data can be accessed while affixed to an object Economically communicates to bus master with a single digital signal at 16.3k bits per second Standard 16 mm diameter and 1-WireTM protocol ensure compatibility with iButton family Button shape is self-aligning with cupshaped probes Durable stainless steel case engraved with registration number withstands harsh environments Easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim Presence detector acknowledges when reader first applies voltage Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class 1, Division 1, Group A, B, C and D locations 1 of 10
F3 MICROCANTM
3.10 0.36 0.51
c 1993
16.25
YYWW REGISTERED RR
66
01
17.35
000000FBC52B
DATA
COMMON iButton FEATURES
GROUND
F5 MICROCANTM
5.89 0.36 0.51
c 1993

16.25
YYWW REGISTERED RR
E6
01
17.35
000000FBD8B3
DATA GROUND
All dimensions shown in millimeters
ORDERING INFORMATION
DS1990A-F3 DS1990A-F5 DS9096P DS9101 DS9093RA DS9093F DS9092 F3 MicroCan F5 MicroCan Self-Stick Adhesive Pad Multi-Purpose Clip Mounting Lock Ring Snap-In Fob iButton Probe
EXAMPLES OF ACCESSORIES
081999
DS1990A
iButton DESCRIPTION
The DS1990A Serial Number iButton is a rugged data carrier that acts as an electronic registration number for automatic identification. The DS1990A consists of a factory-lasered, 64-bit ROM that includes an unique 48-bit serial number, an 8-bit CRC and an 8-bit Family Code (01h). Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return. The DS1990A is fully compatible with the DS1990 Serial Number iButton but provides the additional 1-Wire protocol capability that allows the Search ROM command to be interpreted by the DS1990A and therefore allows multiple DS1990A devices to reside on a single data line. The durable MicroCan package is highly resistant to environmental hazards such as dirt, moisture and shock. Its compact coin-shaped profile is self-aligning with mating receptacles, allowing the DS1990A to be used easily by human operators. Accessories permit the DS1990A to be mounted on plastic key tabs, photo ID badges, printed circuit boards or any smooth surface of an object. Applications include access control, work-in-progress tracking, tool management and inventory control.
OPERATION
The DS1990A's internal ROM is accessed via a single data line. The 48-bit serial number, 8-bit family code and 8-bit CRC are retrieved using the Dallas 1-Wire protocol. This protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. All data is read and written least significant bit first.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master system and one or more slaves. In all instances, the DS1990A is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal type and timing). For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open drain connection or 3-state outputs. The DS1990A is an open drain part with an internal circuit equivalent to that shown in Figure 2. The bus master can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together. The bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figure 3. The value of the pullup resistor should be approximately 5 k for short line lengths. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second. The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset.
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DS1990A
DS1990A MEMORY MAP Figure 1
8-Bit CRC Code MSB LSB MSB 48-Bit Serial Number 8-Bit Family Code (01h) LSB MSB LSB
DS1990A EQUIVALENT CIRCUIT Figure 2
BUS MASTER CIRCUIT Figure 3
To data connection of DS1990A
To data connection of DS1990A
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DS1990A
TRANSACTION SEQUENCE
The sequence for accessing the DS1990A via the 1-Wire port is as follows: Initialization ROM Function Command Read Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1990A is on the bus and is ready to operate. For more details, see the "1-Wire Signaling" section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM function commands. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 4):
Read ROM [33h] or [0Fh]
This command allows the bus master to read the DS1990A's 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1990A on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The DS1990A Read ROM function will occur with a command byte of either 33h or 0Fh in order to ensure compatibility with the DS1990, which will only respond to a 0Fh command word with its 64-bit ROM data.
Match ROM [55h] / Skip ROM [CCh]
The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Match ROM and a Skip ROM command. (See the Book of DS19xx iButton Standards.) Since the DS1990A contains only the 64bit ROM with no additional data fields, the Match ROM and Skip ROM are not applicable and will cause no further activity on the 1-Wire bus if executed. The DS1990A does not interfere with other 1-Wire parts on a multidrop bus that do respond to a Match ROM or Skip ROM (example DS1990A and DS1994 on the same bus).
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual example. 4 of 10
DS1990A
ROM FUNCTIONS FLOW CHART Figure 4
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DS1990A
1-WIRE SIGNALING
The DS1990A requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data. All these signals except presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS1990A is shown in Figure 5. A Reset Pulse followed by a Presence Pulse indicates the DS1990A is ready to send or receive data given the correct ROM command. The bus master transmits (TX ) a reset pulse ( a low signal for a minimum of 480 s). The bus master then releases the line and goes into receive mode (RX ). The 1-Wire bus is pulled to a high state via the 5 k pullup resistor. After detecting the rising edge on the data contact, the DS1990A waits (tPDH , 15-60 s) and then transmits the presence pulse (tPDL , 60-240 s).
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 6. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS1990A to the master by triggering a delay circuit in the DS1990A. During write time slots, the delay circuit determines when the DS1990A will sample the data line. For a read data time slot, if a "0" is to be transmitted, the delay circuit determines how long the DS1990A will hold the data line low overriding the 1 generated by the master. If the data bit is a "1", the iButton will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE "RESET AND PRESENCE PULSES" Figure 5
RESISTOR MASTER DS1990A
480 s tRSTL < * 480 s tRSTH < (includes recovery time) 15 s tPDH < 60 s 60 s tPDL < 240 s
In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 s.
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DS1990A
READ/WRITE TIMING DIAGRAM Figure 6 Write-One Time Slot
60 s tSLOT < 120 s 1 s tLOW1 < 15 s 1 s tREC <
Write-Zero Time Slot
60 s tLOW0 < tSLOT < 120 s 1 s tREC <
Read-Data Time Slot
RESISTOR MASTER DS1990A
60 s tSLOT < 120 s 1 s tLOWR < 15 s 0 tRELEASE < 45 s 1 s tREC < tRDV = 15 s tSU = 1 s 7 of 10
DS1990A
CRC ASSEMBLY LANGUAGE PROCEDURE Table 1
DO_CRC: PUSH PUSH PUSH MOV XRL RRC MOV JNC XRL RRC MOV POP RR PUSH DJNZ POP POP POP RET ACC B ACC B,#8 A,CRC A A,CRC ZERO A,#18H A CRC,A ACC A ACC B,CRC_LOOP ACC B ACC ; save the accumulator ; save the B register ; save bits to be shifted set shift=8bits ; ; calculate CRC ; move it to the carry ; get the last CRC value ; skip if data=0 ; update the CRC value ; ; position the new CRC ; store the new CRC ; get the remaining bits ; position the next bit ; save the remaining bits ; repeat for eight bits ; clean up the stack ; restore the B register ; restore the accumulator
CRC_LOOP:
ZERO:
CRC GENERATION
To validate the data transmitted from the DS1990A, the bus master may generate a CRC value from the data as it is received. This generated value is compared to the value stored in the last eight bits of the DS1990A. The bus master computes the CRC over the 8-bit family code and all 48 ID number data bits, but not over the stored CRC value itself. If the two CRC values match, the transmission is error-free. An example of how to generate the CRC using assembly language software is shown in Table 1. This assembly language code is written for the DS5000 Soft microcontroller which is compatible with the 8031/51 Microcontroller family. The procedure DO_CRC calculates the cumulative CRC of all the bytes passed to it in the accumulator. It should be noted that the variable CRC needs to be initialized to 0 before the procedure is executed. Each byte of the data is then placed in the accumulator and DO-CRC is called to update the CRC variable. After all the data has been passed to DO_CRC, the variable CRC will contain the result. The equivalent polynomial function of this software routine is: CRC = x8 + x5 + x4 + 1 For more details, see the Book of DS19xx iButton Standards.
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DS1990A
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature -0.5V to +7.0V -40C to +85C -55C to +125C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Logic 1 Logic 0 Output Logic Low @ 4 mA Output Logic High Input Load Current Operating Charge SYMBOL VIH VOL VOL VOH IL QOP MIN 2.2 -0.3
(VPUP=2.8V to 6.0V; -40C to +85C)
TYP MAX VCC +0.3 +0.8 0.4 6.0 30 UNITS V V V V A nC NOTES 1,6 1 1 1,2 3 7,8
VPUP 5
CAPACITANCE
PARAMETER I/O (1-Wire) SYMBOL CIN/OUT MIN TYP 100 MAX 800 UNITS pF
(TA = 25C)
NOTES 9
AC ELECTRICAL CHARACTERISTICS
PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL MIN 60 1 60 0 1 480 480 15 60
(VPUP=2.8V to 6.0V; -40C to +85C)
TYP MAX 120 15 120 45 1 UNITS s s s s s s s s s s s NOTES
exactly 15 15
5 4 10
60 240
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DS1990A
NOTES:
1. All voltages are referenced to ground. 2. VPUP = external pullup voltage. 3. Input load is to ground. 4. An additional reset or communication sequence cannot begin until the reset high time has expired. 5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 s of this falling edge and will remain valid for 14 s minimum. (15 s total from falling edge on 1-Wire bus.) 6. VIH is a function of the external pullup resistor and the VCC supply. 7. 30 nanocoulombs per 72 time slots @ 5.0V. 8. At VCC =5.0V with a 5 k pullup to V CC and a maximum time slot of 120 s. 9. Capacitance on the I/O pin could be 800 pF when power is first applied. If a 5 k resistor is used to pull up the I/O line to VCC , 5 s after power has been applied the parasite capacitance will not affect normal communications. 10. The reset low time (tRSTL ) should be restricted to a maximum of 960 s, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses if this device is used in parallel with a DS1994.
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